1. Field of the Invention
The present invention relates to an analog/digital converter (hereinafter referred to as A/D converter), and more particularly to a single chip microcomputer having a built-in A/D converter.
2. Description of the Prior Art
FIG. 4 is a block diagram showing a sequential comparative type A/D converter in a prior art. In FIG. 4, numeral 1 represents an analog input, numeral 2 represents a comparator, numeral 3 represents a CPU for controlling, numeral 4 represents a register for storing ending flag, numeral 5 represents a SAR (serial approximation register), numeral 6 represents a D/A converter as a reference voltage generator, numeral 7 represents an interrupt request signal, and numeral 8 represents a reference voltage output (Vref) for comparing. The A/D converter is of 10 bits. Numeral 9 indicates a digital parallel output signal and numeral 10 indicates a data bus.
The SAR 5, for example, is provided with a shift register 11 of 10 bits and counts comparing steps from the most significant bit to the least significant bit. At every proceeding of the comparing bits, count value of the shift register 11 also increases to the right direction, and outputs a carry flag F to the register 4 when the comparisons of the 10 bits are terminated. The SAR 5 outputs an interrupt signal 7 after the termination of A/D conversion.
Next, the operation will be explained referring to timing charts in FIGS. 5 and 6. In the sequential comparative type A/D converter, the comparisons with the analog input 1 are performed one bit by one bit starting from the most significant bit in the SAR 5. At the time when the comparisons of all bits are terminated, the ending flag F is set in the register 4 and outputs an interrupt request signal E if necessary. FIG. 5 is a timing chart showing a case where the ending flag F is used. The CPU 3 polls the ending flag F with a pulse C of its own bus cycle T, and reads out a digital signal (conversion result) after the termination is confirmed. On the other hand, a clock of the A/D converter is of a cycle t as shown at a pulse D, and the shift register 11 shifts with this clock speed. The relationship between the cycle T of the polling pulse C and the cycle t of the clock pulse D is T&gt;2t and the clock frequency of the A/D converter is made to be high. FIG. 6 is a timing chart showing a case where the interrupt is used. After the A/D conversion is terminated, the interrupt request signal E is outputted. The CPU 3 branches into interrupt routines after saving of necessary contents of the register to the stack. The necessary minimum time P is consumed for saving the register, and the digital signal 9 is read out in the interrupt routine.
Since the conventional A/D converter is constructed as the above description, when the ending flag F is to be polled by the bus cycle as shown in FIG. 5, a delay time more than 1 bus cycle (1t) at the lowest will be generated until the digital output signal is read out after termination of the A/D conversion (10t). Since the flag F is confirmed with a leading read out pulse a and the digital signal 9 is read out actually with next read out pulse b, a delay T.sub.D over the cycle T is generated actually. Dependent on instruction system of the CPU 3, an operation code fetch occurs after the read-out of the ending flag F until the digital signal 9 is read out, so that there is possibility to produce a large delay time. Also in the case where the interrupt request signal E is to be used as shown in FIG. 6, a larger delay time T.sub.P will be generated since the minimum pulse width for register saving is P.